1. Field
Embodiments of the present general inventive concept relate to a non-volatile memory device.
2. Description of the Related Art
When a read operation is performed in a non-volatile memory device, e.g., electrically erasable programmable read-only memory (EEPROM), with a large capacity, data is read in bulk from a plurality of memory cells in a page at one time and output in series. When a write operation is performed on memory cells, data of a page is input in series to the non-volatile memory device and it is written in bulk to a plurality of memory cells at one time. To perform the read or write operation, a plurality of columns, i.e., bit lines are connected to a page buffer including a data latch that temporarily latches data to be read or written.
In NAND-type EEPROM, a write operation is performed on memory cells in a row among a plurality of memory cells arranged in a matrix form of rows and columns. In general, a NAND-type EEPROM cell is a floating gate N-channel metal oxide semiconductor (NMOS) transistor formed in a P-type well at a surface of a semiconductor substrate. The floating gate NMOS transistor includes a source region and a drain region separated from each other in the P-type well, a tunnel oxide layer formed in a channel region between the source region and the drain region, a floating gate formed of polycrystalline silicon on the tunnel oxide layer, and a control gate formed of a dielectric layer on the floating gate.
Memory cells in a column in the matrix form are connected in series with each other, forming a NAND cell string. A first selection transistor is disposed between a first end of the NAND cell string and a bit line and a second selection transistor is disposed between a second end of the NAND cell string and a common source line.
In a write operation, the first selection transistor is turned on and the second selection transistor is turned off, and simultaneously a voltage of 0 V is applied to a bit line when data of 0 is written and a power supply voltage is applied to the bit line when data of 1 is written (when an erased state is maintained). In addition, a program voltage is applied to a word line connected to a selected memory cell and a write-inhibit voltage is applied to a word line connected to an unselected memory cell.
Therefore, a high voltage is applied between a channel and a control gate in a memory cell to which data of 0 is written, so that electrons are injected from the channel to a floating gate. As a result, a threshold voltage of the memory cell shifts from a negative voltage to a positive voltage. Meanwhile, a lower voltage is applied to a channel and a control gate in a memory cell to which data of 1 is written, so that injection of electrons to a floating gate is suppressed. As a result, a threshold voltage of the memory cell is maintained negative.
However, as described above, data is written using tunnel current in NAND-type EEPROM, and therefore, a data write speed is different among memory cells. Accordingly, even through all memory cells have the same write time, some memory cells have a threshold voltage in a normal range of at least 0 V and less than a predetermined voltage (e.g., 5 V) while other memory cells have a threshold voltage greater than the predetermined voltage.
In a read operation of the NAND-type EEPROM, the predetermined voltage (hereinafter, referred to as a read voltage) is applied to the word line connected to the unselected memory cell to turn on the memory cells, but when the memory cell has a threshold voltage greater than the predetermined voltage, the memory cell remains as an off-cell. Therefore, a current path in the NAND cell string is cut off due to the memory cell (that remains as the off-cell), so that data cannot be read from other memory cells connected in series with the memory cell in the NAND cell string.
To solve this problem, approaches for using a cycle of writing, write-verification, and data setup for rewriting in a write operation have been introduced. For a memory cell with a satisfactory threshold voltage, a rewrite data (i.e., data “1”) is set at a data latch in a page buffer by the write-verification so that data “0” is not written to the memory cell in a subsequent cycle.
When the write operation is configured as described above, writing to a memory cell with a high write speed is completed quickly, thereby preventing the threshold voltage of the memory cell from increasing afterward. As such, writing and write-verification are continued until data of page is written to all selected memory cells in the NAND-type EEPROM.
In such NAND-type EEPROM, a voltage of a common source line increases and then decreases due to cell current in a read operation or a write-verify operation. Time during which the voltage of the common source line decreases increases as the number of cells (i.e., on-cells) having data of 1 in a page in a column direction increases. As a result, the potential of a bit line does not decrease until the potential of the common source line decreases satisfactorily, and therefore, it is difficult to precisely detect a memory cell state (i.e., on-cell or off-cell) from a latch of a page buffer connected to the bit line.
A technique of detecting a memory cell state even when a voltage of a common source line increases is disclosed in Japanese Patent Laid-open Publication No. 11-96783. A non-volatile memory device disclosed in Japanese Patent Laid-open Publication No. 11-96783 adjusts a voltage of a selected word line based on a voltage of a common source line in a memory cell array during a read operation or a write-verify operation.
In detail, the non-volatile memory device disclosed in Japanese Patent Laid-open Publication No. 11-96783 increases a voltage of a selected word line when the voltage of a common source line increases, thereby easily turning on a selected memory cell with a threshold voltage increased as a memory cell to which data “1” is written. As a result, a bit line connected to the selected memory cell is discharged, making it possible to correctly input the data “1” from the selected memory cell to a page buffer. However, even though the data is correctly input to the page buffer, since a latch in the page buffer detects the data, the data input to the page buffer may be erroneously detected unless the timing of the latch is controlled.
When there is a great number of 1s, for example, when all of memory cells in a page are on-cells, the decreasing time of the voltage of the common source line is longest. Time for which the potential of a bit line decreases (hereinafter, referred to as a bit line development) also increases. Accordingly, it is necessary to delay the timing of data input to a page buffer connected to the bit line and data detection by a latch of the page buffer following the bit line development to be suitable for a case where there are a great number of 1s in order to prevent erroneous data detection. Consequently, time for which data is read from the page buffer is set long.